The present invention relates to a semiconductor device and a method for manufacturing the same.
A semiconductor memory devices is constructed of a plurality of unit cells, each including one capacitor and one transistor. The capacitor is used to temporarily store data. The transistor is used to transfer data between a bit line and the capacitor according to a control signal using the characteristics of a semiconductor changing an electric conductivity according to an environment. The transistor is composed of three regions including a gate, a source, and a drain. Charge transfer occurs between the source and the drain according to a control signal input to the gate. The charge transfer between the source and the drain is achieved through a channel region using the characteristics of the semiconductor.
When a transistor is manufactured on a semiconductor substrate, a gate is formed on the semiconductor substrate, then impurities are doped on both sides of the gate to form a source and a drain.
As a data storage capacity of the semiconductor memory device is increased and the semiconductor memory device becomes highly integrated, there is a need to reduce the size of unit cells. Namely, since a design rule of the capacitor and the transistor included in the unit cell is decreased, and accordingly a channel length of a cell transistor is gradually reduced, a short channel effect and Drain Induced Barrier Lower (DIBL) occurs in a general transistor to thereby deteriorate the reliability of an operation. These phenomena occurring due to a reduction in channel length can be solved by maintaining a threshold voltage so that the cell transistor may perform a normal operation. In general, the shorter the channel of the transistor is, the larger a doping density of impurities in a channel formation region is.
However, when the design rule is reduced to less than 100 nm, doping densities in a channel formation region is increased by as much as this. This increases an electric field in a storage node (SN) junction to thereby deteriorate a refresh characteristic of the semiconductor memory device as the occurrence of another problem. To solve the problem, a cell transistor having a 3-dimensional channel structure is used in which a channel is formed in a vertical direction so that a channel length of a transistor can be maintained in spite of a reduction in the design rule. Namely, although a channel width in a vertical direction is short, the doping density can be reduced as much as a channel length in the vertical direction is secured, thereby preventing the refresh characteristic from being deteriorated.
In addition, the higher integration of a semiconductor device, the shorter a distance between a word line and a bit line connected to a cell transistor. Owing to this, parasitic capacitance is increased to deteriorate an operation margin of a sense amplifier amplifying data transferred through the bit line. The parasitic capacitance also has a bad influence upon the operation reliability of a semiconductor device.
To solve such a problem, a buried word line structure has been proposed to reduce parasitic capacitance between a bit line and a word line. In the buried word line structure, the word line is formed in only a recess and not at an upper portion of a semiconductor substrate. In the buried word line structure, a conductive material is formed in the recess formed in the semiconductor substrate, and an upper portion of the conductive material is covered with an insulating layer to bury the word line in the semiconductor substrate. Accordingly, an electric isolation with the bit line formed on the semiconductor substrate on which source/drain are disposed can be clearly achieved.
As described above, in the buried word line structure, the area in which the source/drain junction and the word line are overlapped exists and Gate Induced Drain Leakage (GIDL) is generated in such an overlapped area. If the GIDL is large, the stored electric charge is discharged, and memory retention characteristics are degraded.